Imagination opens up its MIPS architecture to universities
Imagination Technologies, which has two design centres in the SouthWest region, is opening up its MIPS architecture to universities with the RTL implementation of a simplified microAptiv design.
MIPSfpga gives universities around the globe free and open access to a fully-validated, current generation MIPS CPU in a complete teaching package that can be run in a low cost FPGA. The core is already popular in the PIC32MZ microcontroller from Microchip Technology but access to the detailed RTL – the code that implements the core – can be tremendously helpful for teaching.
CPU architecture is generally taught as part of electronic engineering, computer science and computer engineering courses. Until now, what’s been missing from all of these courses is access to real, un-obfuscated RTL code that will enable professors and students to study and explore a real CPU. RTL code is often hidden, or obfuscated, to prevent it being copied and used in other designs without paying royalties or license fees to the original developer.
How a design is implemented into silicon
The MIPS architecture was originally developed at Stanford University in the early 1980s. It has been the teaching architecture of choice for decades because of its elegant true RISC design, epitomized by Dr. David A. Patterson and Dr. John L. Hennessy in their book, ‘Computer Organization and Design’, now in its fifth edition.
The MIPS CPU is being offered as part of a complete free-to-download package for universities, together with a Getting Started Guide, teaching guide for professors, and examples designed to enable students to see how the CPU works and explore its capabilities. With the materials, students can develop a CPU and take it through debug, running on an FPGA platform.
This MIPS CPU configuration is designed to run on a low-cost FPGA platform, with guides available for the Digilent Nexys4 platform with a Xilinx Artix-7 FPGA, and the Terasic DE2 platform with an Altera Cyclone FPGA.
MIPSfpga is already running in several academic institutions including Harvey Mudd College, Imperial College London, University College London (UCL), and the University of Nevada, Las Vegas (UNLV).
The variant of the MIPS microAptiv core that is used for MIPSfgpa
The MIPSfpga CPU and related materials are available for download from the Imagination University Programme website now for first phase users via an application process. Academics can register at http://community.imgtec.com/university.
Phase two, starting in June, will require only a simple click-through agreement. Additional teaching materials are being developed and will be made available later this year.
However, the programme is not entirely open source. For academic users the license is simple: you can use it as you wish, but you cannot put it into silicon. If you modify it, you must talk to Imagination first if you wish to patent the changes. In summary, universities can go as deep as they like under the hood to explore how today’s complex CPUs are built.
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Imagination’s potential to really take on Raspberry Pi
Does the electronics industry need another low cost development board? After all, we already have nearly 1.5m Raspberry Pi boards shipped worldwide, as well as a plethora of Arduino and Beagle boards. There’s even the Galileo boards from Intel using the low cost, low power x86 X1000 Quark processor.
Imagination Technologies, which has a design centre in Bristol and its wireless division nearby in Chepstow and is a key player for technology in the region, has developed its own version of Raspberry Pi. The Creator C120 uses a MIPS-based processor from Ingenic and is the first board that combines Imagination’s MIPS, PowerVR and Ensigma programmable RF technologies.
The 90.2 mm x 95.3 mm board uses an Ingenic JZ4780 with a 1.2GHz dual core 32bit MIPS with a SIMD engine (for doing graphics quickly) and both single and double precision floating point FPU. It is also adding 802.11 b/g/n WiFi and Bluetooth 4.0 connectivity. For video and graphics, the PowerVR SGX540 GPU and dedicated video hardware support a suite of video codecs, including MPEG-4, H.264, VP8, MPEG-2, RV9, and others. There’s also two USB ports and an HDMI connector – there’s more details and comments on the background in the EETimes story I wrote.
The other interesting thing is to look forwards. Imagination has pointed out that this first board doesn’t use its Ensigma IP – what about a low cost Ingenic part with the Whisper WiFi IP (more on that here tomorrow!) and Warrior processor embedded as well? A low cost board with good WiFI out of the box running Android 4.4 KitKat? That is a compelling coder/developer board at $25-$35 that would also make a huge difference to ODMs – and don’t forget Imagination has a well established consumer electronics subsidiary (Pure) that already has volume board manufacturing deals. Add in Imagination’s Flow cloud software on this to make it easily part of a home system with some automatic discovery and it becomes compellingly easy to set up and use. Mmmmmmm, some very interesting opportunities there!
Imagination Takes On Raspberry Pi | EE Times.
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Ensigma’s 802.11ac WiFi IP cores gain chip traction
There is growing market traction for the Ensigma Series4 ‘Explorer’ radio processor unit (RPU) cores designed in Chepstow as more companies integrate 802.11ac WiFi, Bluetooth 4.1 and other connectivity into their Systems-on-Chips (SoCs).
New customers for the Ensigma WiFi/Bluetooth combo IP cores from Imagination Technologies include Ineda, Toshiba, Toumaz and multiple fabless companies from Korea and China including Rockchip and others from around the world who will be announced publicly at a later time. Among the target applications are streaming media devices, tablets, wearables, IoT devices and standalone WiFi combo chips. The new Ensigma WiFi licensees join the growing Ensigma RPU customer base, which also includes Qualcomm, STMicroelectronics, S2-Tek, Frontier Silicon, Orca Systems and others.
“Moving forward, virtually every device will be connected,” said Martin Woodhead, EVP for Ensigma Communications at Imagination. “To address this, the Ensigma RPU offers the flexibility to design for a range of connectivity and broadcast standards using just one on-chip radio system, so customers can create one design for multiple markets and also have a built-in roadmap for emerging standards. With our end-to-end connectivity solutions including RF, baseband, firmware, software, support and certifications, Imagination is uniquely positioned to help customers address new market opportunities quickly and cost-effectively.”
Imagination has a graphics hardware and software design centre in Bristol as well as the radio design team in Chepstow. The company’s program of WiFi Alliance certifications ensures interoperability. Imagination has recently achieved WiFi Alliance certification for Miracast and Passpoint, adding to a growing list of certifications including WiFi CERTIFIED, WiFi Direct, WPA, WPA2, WMM and WiFi Protected Setup.
The Ensigma Series4 RPUs provide a unique universal and highly scalable solution for integrating global connectivity and broadcast communications capabilities into SoCs. By combining the latest software programmable radio techniques with a multi-processor architecture, a wide range of communications standards are fully supported. The flexible hardware architecture of Ensigma Series4 RPUs means that the engine can be easily scaled to address everything from the smallest most cost-sensitive embedded connected processors to the most advanced connected smart TVs and tablets targeting global markets.
Ensigma RPUs support all key standards for connectivity including 802.11a/b/g, 802.11n with up to 4×4 MIMO, 802.11ac with up to 2×2 MIMO, as well as Bluetooth. They also enable global TV products supporting DVB-T2, DVB-T, ISDB-T, ATSC, GB20600-2006 (CTTB), DVB-S2, DVB-S, ISDB-S, DVB-C, J.83B, ISDB-C; analogue TV; mobile TV including T-DMB, 1-Seg ISDB-T; and broadcast radio standards including DAB/DAB+, HD Radio, 3-seg ISDB-T, ISDB-Tmm and FM.
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Leading multicore silicon conference set for September in Bristol
Multicore Challenge Conference 2012
24 September 2012
Bristol (UWE, French Campus)
TVS and ICT KTN are holding the 2012 Multicore Challenge Conference on Monday, 24 September 2012 with speakers, case studies, workshops and tool demonstrations on the latest techniques and technologies for developing systems with multiple processor and graphics cores.
Leading speakers from Imagination, Intel and the University of Bristol will also be part of a panel session at the end of the day on the challenges of developing and using multicore silicon chips. Sign up here
Provisional agenda for the Multicore Challenge Conference 2012
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